Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the semiconductor structures has provided significant improvement in the speed, performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges, however, are faced as the sizes of CMOS devices continue to decrease.
One such challenge is soft errors. Soft errors are errors that occur in the logic state of a circuit due to excess charge carriers, which are typically induced by alpha-particles and cosmic ray neutrons. As the excess charge carriers are induced into a circuit, the logic values may be altered. For example, a logic value of a capacitor or line may be altered from a logic “0” to a logic “1, ” transistor gates may be turned off or on, or the like. Soft errors occurring in SRAM devices or other memory devices can cause the stored data to become corrupted.
Attempts have been made to limit the effect of excess charge carriers and soft errors on integrated circuits. One such attempt involves the addition of error-correcting circuitry (ECC). Another attempt involves increasing the cell size to increase the capacitance of charge nodes, thereby decreasing the effect of excess charge carriers. Yet another attempt requires additional capacitance, such as a MIM structure, trench capacitor, stack capacitor, or the like, to be added to the charge node. Yet another attempt involves increasing the resistance between the source/drain areas of the charge node and the gate of the charge node. Yet other attempts involve reducing the well resistance and/or increasing the well strapping frequency.
These attempts, however, generally require additional circuitry, additional processing, increased power requirements, and/or increased sizes, which may adversely affect the design and fabrication of smaller, more power-efficient integrated circuits.
Therefore, there is a need for an integrated circuit that is more resilient to soft errors and excess charge carriers.